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Электронный компонент: LAN83C171

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LAN83C171
ADVANCE INFORMATION
LAN83C171 - EPIC/XF
ACPI/PC 97 Compliant Integrated PCI 10/100
Mbps Fast Ethernet Controller
FEATURES
IEEE 802.3 Compatible 10/100 Mbps Fast
Ethernet Controller
Fully Compliant Glueless PCI Version 2.1
Bus Interface
Support Included for CardBus Status
Registers
PCI Universal 3V/5V Output Drives
Preemptive Interrupt Support for Efficient
Network Packet Processing
High Performance Two Channel Bus Master
(132 Mbps)
Scatter/Gather DMA Capability
Programmable Burst Length Counter
ACPI Compliant for
-
PCI Bus Class Specification
-
Network Device Class Specification
PC 97 Compliant
Wake-Up on Magic Packet
TM
Detection
and/or Network Link-Down Occurrence
Special Low Power State Mode For
Scanning Magic Packets
TM
Upon PCI Bus
Power Loss
Supports Chaining of Transmit Packets
Optional Early Transmit and Early Receive
Optional Receive Lookahead Buffering
Mode
Automatic Rejection of Runt Packets
Automatic Retransmission of Collision
Frames from Internal Buffer
Automatic Padding of Short Frames
4.5 Kbyte On-Chip Receive Buffer and 1.5
Kbyte On-Chip Transmit Buffer Eliminate
Bus Latency Issues
Optional Variable Depth, 32 Bit Wide
External Receive Buffer (0, 16, 32 or 128
Kbytes)
Big or Little Endian Byte Ordering
Capable of Supporting 64 Kbyte Expansion
Boot Flash RAM
IEEE Standard MII Interface to Physical
Layer
Interface to LAN83C694 - Shares MII Pins
Serial MII Management Interface
Serial EEPROM Interface for Storage of
LAN Address and Configuration Information
On-Chip Clock Multiplier
Low Power Sleep Mode
Support for Full Duplex Ethernet
Internal and External Loopback Diagnostic
Functions
Simple I/O Pin Mapping Scheme to
Facilitate In-Circuit Test
Single 5V Power Supply
208 Pin QFP Package
Software Drivers to Operate with Major
Operating Systems, Including:
-
NDIS 3.4 and 5 for Microsoft
-
DOS ODI for Novell
2

GENERAL DESCRIPTION
The LAN83C171 EPIC/XF is a high-performance
and a low CPU utilization Ethernet network
controller designed to interface directly to the
PCI Local Bus on one side and to the 802.3
standard Media Independent Interface (MII) on
the other side. The network interface can also
be configured to communicate directly with the
LAN83C694 10BASE-T transceiver.

The LAN83C171 implements 802.3 Media
Access Control functions. It is capable of
running at Ethernet rates of both 100Mb/s and
10Mb/s. An MII compliant serial management
interface is provided to control external media
dependent transceivers. The LAN83C171 is a
two channel bus master (one for transmit, one
for receive) capable of transferring data at the
maximum PCI transfer rate of 132Mbps. The
LAN83C171 has several features designed to
minimize CPU utilization, including the optional
Receive Lookahead Buffering Mode, which
eliminates the need to re-copy the data from one
host memory location to another.
3

TABLE OF CONTENTS
FEATURES ........................................................................................................................................1
GENERAL DESCRIPTION .................................................................................................................2
PIN CONFIGURATION.......................................................................................................................5
DESCRIPTION OF PIN FUNCTIONS .................................................................................................6
FUNCTIONAL DESCRIPTION..........................................................................................................10
PCI INTERFACE..........................................................................................................................12
TRANSMIT/RECEIVE ARBITRATION FOR PCI BUS .................................................................12
SYSTEM ERRORS ......................................................................................................................12
BIG/LITTLE ENDIAN SUPPORT ..................................................................................................12
POWER DOWN MODE ....................................................................................................................14
DMA OPERATION .......................................................................................................................14
TRANSMIT DMA..............................................................................................................................14
Direct Queuing Method.................................................................................................................14
Fragment List Method ..................................................................................................................16
Interrupting Transmit Chain..........................................................................................................18
Transmit Buffer Full .....................................................................................................................18
Transmit Underrun .......................................................................................................................18
Exception to Underrun ReTransmission........................................................................................18
Maximum Transmit Size and Burst Rate.......................................................................................18
RECEIVE DMA.................................................................................................................................19
Free Buffer Pool Method...............................................................................................................19
Adding Receive Buffers to the Pool...............................................................................................20
Receive Lookahead Method .........................................................................................................20
Stopping the Receive DMA...........................................................................................................25
Maximum Receive Size and Burst Rate ........................................................................................25
MAC OPERATION ...........................................................................................................................26
MII MANAGEMENT INTERFACE .................................................................................................32
EEPROM INTERFACE.................................................................................................................32
JUMPER OPTIONS (EEPROM/RAM)...........................................................................................33
Advanced Configuration and Power Interface (ACPI) Support .......................................................33
Wake-Up Events and Notification .................................................................................................33
EPIC Power States.................................................................................................................34
D3(Cold1) Software Driver Requirements .....................................................................................35
Supporting Power Management Options.......................................................................................35
PME Generates a PCI Bus Interrupt .............................................................................................35
Initial Power-On Reset (POR).......................................................................................................35
Special Power Management Mode................................................................................................36
POWER DOWN MODE ...............................................................................................................36
SOFT RESET ..............................................................................................................................37
CONFIGURATION ...........................................................................................................................37
Mapping of Control Functions.......................................................................................................37
Mapping of Flash RAM Functions.................................................................................................37
DMA DESCRIPTOR BITS DESCRIPTION........................................................................................39
TRANSMIT DMA DESCRIPTOR BITS DESCRIPTION .................................................................39
RECEIVE DMA DESCRIPTOR BITS DESCRIPTION....................................................................41
CONTROL REGISTER MAP/REGISTERS DECODE........................................................................43
CONFIGURATION REGISTERS MAP..............................................................................................44
4
CONTROL REGISTERS BITS DESCRIPTION .................................................................................45
PCI CONFIGURATION REGISTERS BITS DESCRIPTION...............................................................64
OPERATIONAL DESCRIPTION .......................................................................................................70
Maximum Guaranteed Ratings .....................................................................................................70
DC Electrical Characteristics ........................................................................................................70
TIMING DIAGRAMS ........................................................................................................................72








































80 Arkay Drive
Hauppauge, NY 11788
(516) 435-6000
FAX (516) 273-3123

5

PIN CONFIGURATION
LAN83C171
208 Pin QFP
VSSC
VDDAC
VSSAC
SYSCLK
VDDC
RXD3
TXD0
TXD1
TXD2
TXD3
TX_EN
nPHYRST
n694EN
VSSC
MDC
MDIO
VDDC
n694LNK
TEST
GPIO2/PHY_INT
GPIO1
nINTA
nRST
VDDC
PCICLK
VSSC
VSSG
nCLKRUN
nGNT
VDDIO
nREQ
AD31
VSSPC
VDDIO
VSSG
AD30
AD29
VDDIO
AD28
AD27
VSSPC
AD26
AD25
VSSIO
AD24
nCBE
VSSPC
IDSEL
AD23
VDDIO
VSSPC
VDDIO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
VDDC
VSSAC
VDDAC
MD10
MD9
MD8
MD7
MD6
MD5
MD/JMP4
MD/JMP3
MD/JMP2
MD/JMP1
MD/JMP0
VSSAC
VDDAC
MA15/nRAMWR
EESK/MA14
EEDI/MA13
MA12
MA11
MA10
VSSC
MA9
MA8
VDDC
VSSAC
VDDAC
MA7
MA6
VSSC
MA5
MA4
MA3
MA2
MA1
MA0
VSSIO
AD0
AD1
VDDIO
AD2
AD3
VSSPC
AD4
AD5
VDDC
AD6
AD7
VDDIO
VSSPC
VDDIO
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
2
0
8
2
0
7
2
0
6
2
0
5
2
0
4
2
0
3
2
0
2
2
0
1
2
0
0
1
9
9
1
9
8
1
9
7
1
9
6
1
9
5
1
9
4
1
9
3
1
9
2
1
9
1
1
9
0
1
8
9
1
8
8
1
8
7
1
8
6
1
8
5
1
8
4
1
8
3
1
8
2
1
8
1
1
8
0
1
7
9
1
7
8
1
7
7
1
7
6
1
7
5
1
7
4
1
7
3
1
7
2
1
7
1
1
7
0
1
6
9
1
6
8
1
6
7
1
6
6
1
6
5
1
6
4
1
6
3
1
6
2
1
6
1
1
6
0
1
5
9
1
5
8
1
5
7
N
/
C
V
S
S
C
V
S
S
C
V
D
D
C
X
2
0
V
S
S
A
B
I
A
S
Z
E
N
E
R
V
D
D
A
R
X
D
2
R
X
D
1
R
X
D
0
C
R
S
C
O
L
R
X
_
C
L
K
R
X
_
D
V
R
X
_
E
R
V
D
D
C
T
X
_
C
L
K
V
S
S
C
n
R
O
M
C
S
E
E
C
S
n
R
A
M
O
E
n
R
A
M
C
S
V
S
S
A
C
E
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D
O
/
M
D
3
1
V
D
D
A
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n
R
O
M
W
E
V
S
S
A
C
V
S
S
C
V
D
D
C
N
/
C
M
D
2
5
M
D
1
9
M
D
1
8
M
D
2
0
M
D
1
5
M
D
1
3
M
D
1
1
M
D
1
4
M
D
2
6
M
D
2
4
M
D
1
7
M
D
2
1
M
D
1
6
M
D
2
3
M
D
1
2
M
D
2
2
M
D
3
0
M
D
2
9
M
D
2
8
M
D
2
7
V
S
S
P
C
n
P
M
E
V
D
D
I
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V
S
S
P
C
V
D
D
I
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V
S
S
A
A
D
2
2
A
D
2
1
A
D
2
0
V
S
S
P
C
A
D
1
9
A
D
1
8
A
D
1
7
V
D
D
I
O
A
D
1
6
n
C
B
E
2
V
S
S
P
C
n
F
R
A
M
E
n
I
R
D
Y
V
D
D
I
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V
S
S
C
n
T
R
D
Y
n
D
E
V
S
E
L
V
S
S
P
C
n
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T
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P
V
S
S
G
n
L
O
C
K
V
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S
I
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V
D
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C
V
S
S
P
C
n
P
E
R
R
n
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R
R
V
D
D
I
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P
A
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n
C
B
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1
A
D
1
5
A
D
1
4
V
S
S
P
C
A
D
1
3
A
D
1
2
A
D
1
1
A
D
1
0
V
D
D
I
O
A
D
9
A
D
8
V
S
S
C
n
C
B
E
0
V
S
S
G
V
D
D
I
O
V
S
S
P
C
V
D
D
I
O
V
S
S
P
C
5
3
5
5
5
6
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6
4
6
5
6
6
6
7
6
8
6
9
7
0
7
1
7
2
7
3
7
4
7
5
7
6
7
7
7
8
7
9
8
0
8
1
8
2
8
3
8
4
8
5
8
6
8
7
8
8
8
9
9
0
9
1
9
2
9
3
9
4
9
5
9
6
9
7
9
8
9
9
1
0
0
1
0
1
1
0
2
1
0
3
1
0
4
5
4